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? semiconductor components industries, llc, 2018 january, 2018 ? rev. 0 1 publication order number: ncp12600/d ncp12600 multi-mode controller for offline power supplies the ncp12600 is a peak?current controller operating at a 65?khz or 100?khz fixed frequency. in high power conditions, the part operates in continuous conduction mode (ccm). as the load current reduces, the converter enters the discontinuous conduction mode (dcm) of operation and synchronizes the turn?on event with the minimum of the drain voltage. the ncp12600 implements valley switching mode with a proprietary lockout scheme ensuring noise?free operations. as output power further reduces, the controller folds the switching frequency back and ensures stable valley switching operations down to the 32 nd valley provided the ringing is of suf ficient amplitude. the controller then enters a proprietary quiet?skip skip?mode at small peak currents which reduces acoustic noise and optimizes no?load standby power. adjustable over power protection ensures a flat output power level regardless of the operating input voltage. slope compensation is ensured via the insertion of a resistor in series with the current sense pin and is thus user?adjustable. the device packs several useful features such as an extremely fast short circuit protection, a soft start in current and frequency plus a dedicated circuitry to avoid latch off in case of a line cycle dropout. over temperature protection (otp) is implemented at the current sense pin and requires the connection of a simple ntc resistance to the auxiliary winding. over voltage protection (ovp) is done by sampling the auxiliary plateau and exists at the v cc pin level. features ? 65?khz or 100?khz fixed?frequency operation ? valley switching in discontinuous conduction mode for improved efficiency ? proprietary valley lockout for controlled operation in quasi?resonant operation and foldback modes ? proprietary quiet skip mode for noiseless operation in light load ? adjustable over power protection ? single 64?ms protection timer or dual ocp protection in option ? frequency foldback down to 25 khz ? auto?recovery or latched overload protection ? true output short circuit protection with pre?short compatibility ? line cycle dropout recovery in latched ocp mode ? 5?ms soft start on both peak current and frequency for lower start?up stress ? frequency jitter in all operating modes ? over voltage protection with precise auxiliary voltage sampling event ? over temperature protection combined on cs pin ? ultra?low start?up current below 10 a up to 125 c t j ? proprietary quick latched?state reset scheme ? these are pb?free and rohs?compliant devices typical applications ? ac?dc notebook adapters, usb adapters, w all?mount power supplies, set top boxes, etc. pin connections 1 3 cs gnd 2 zcd/fault 4 drv 6 (top view) 5 v cc tsop?6 (sot23?6) sn suffix case 318g style 13 marking diagram fb www. onsemi.com (note: microdot may be in either location) 1 6zvayw 1 6zvayw = specific device code z = a or 2 (frequency) v = e, f, g or h a = assembly location y = year w = work week = pb?free package see detailed ordering, marking and shipping information on page 3 of this data sheet. ordering information
ncp12600 www. onsemi.com 2 figure 1. typical application schematic 1 2 3 6 4 5 vbulk . . vout . ncp12600 slope compensation otp opt. table 1. pin description pin no pin name function pin description 1 gnd ? the controller ground. 2 fb feedback pin feedback input for the controller. allows direct connection to an optocoupler. 3 zcd/ opp/ fault detects core reset in qr operation. latches off the part in ovp. adjusts opp level. a resistive bridge from this pin to the auxiliary winding adjusts the opp level and lets the controller observe the core magnetic state. a precise ovp level can also be set via this pin. 4 cs current sense this pin monitors the primary peak current but also offers a means to ad- just the compensation ramp level. a ntc connected to the pin offers a simple over temperature protection. 5 v cc supplies the controller this pin is connected to an external auxiliary voltage and features an over voltage protection circuitry. 6 drv driver output the driver?s output to an external mosfet gate. it is clamped to a safe 12?v gate?source level. options forming the part?number : ncp12600xyzsn65t1g ? 65?khz version with xyz picked up in the below list ncp12600xyzsn100t1g ? 100?khz version with xyz picked up in the below list the following code is adopted for the three letters x, y and z: x implies the following choice : a = single ocp b = dual?level ocp level y is the protection scheme : a = all protections are latched: ovp on demag, v cc ovp, otp on cs, overload (ocp) and short circuit (scp) b = overload (ocp) and short circuit (scp) are in auto?recovery mode, all other protections (ovp on demag, v cc ovp, otp on cs) are latched c = all protections are in auto?recovery: ovp on demag, v cc ovp, otp on cs, overload (ocp) and short circuit (scp) z implies the following options : a = quiet skip b = normal skip mode 600 x y y part ocp trip point ocp fault quiet skip a ? single, v cs = 0.7 v (max i p ) a ? all latched a ? yes b ? dual, v cs = 0.5 v (overload), v cs = 0.7 v (max i p ) b ? sc/ocp autorecovery, rest is latched c ? all autorecovery b ? no c to z ? reserved
ncp12600 www. onsemi.com 3 ordering information controller marking freq. (khz) ocp scp ovp aux otp cs ovp v cc mode skip package shipping ncp12600aaasn65t1g 6ae 65 l l l l s q tsop6 (pb?free ) 3000 / tape & reel ncp12600abasn65t1g 6af 65 ar l l l s q ncp12600abbsn65t1g 6ag 65 ar l l l s n ncp12600acbsn65t1g 6ah 65 ar ar ar ar s n NCP12600AAASN100T1G 62e 100 l l l l s q ncp12600abasn100t1g 62f 100 ar l l l s q ncp12600acbsn100t1g 62g 100 ar ar ar ar s n ar auto?r ecovery : the controller enters hiccup mode and tries to resume operations l latched : the controller is latched and the user needs to cycle the input voltage to restart ocp over current protection : the power supply is overloaded scp short circuit protection : the power supply output is short circuited mode single (s) or dual (d) trip point in overload skip normal (n) or quiet skip (q) rfb + ? + ? + ? skip jitter in dcm + leb + ? votp + vilim + ? + ? + ? vzcd 400 mv vovp1 1.5 us blanking zcd fb cs slope comp. rramp max ip skip 60mv always neg. or 0 dcm? dmg jitter in ccm ovp1 bo? s r q q otp qb qb fb fb vdd ovp1 otp vcc + ? ovp2 uvlo fixed fsw or vco clock reset slow clock clamp vcc gnd in out drv multi?mode management fixed frequency or valley lockout operation fault management timers, uvlos vcc discharge 1.5 us blanking figure 2. internal block diagram
ncp12600 www. onsemi.com 4 table 2. maximum ratings table symbol rating value unit v cc power supply voltage, vcc pin, continuous voltage ?0.3 to 28 v v drv(tran) drv pin voltage, transigent voltage (note 1) ?0.3 to v cc + 0.3 v v cs , v fb , v zcd maximum voltage on low power pins cs and fb ?0.3 to 5.5 v v zcd(trann) maximum negative transient voltage on zcd pin (note 2) ?1 v v zcd(tranp) maximum positive transient voltage on zcd pin ( 2) 7 v i source,max maximum sourced current, pulse width < 800 ns 0.6 a i sink,max maximum sinked current, pulse width < 800 ns 1.0 a i zcd maximum injected negative current into the zcd pin (pin 1) ?2 ma r j?a thermal resistance junction?to?air 360 c/w t j,max maximum junction temperature 150 c storage temperature range ?60 to +150 c hbm human body model esd capability per jedec jesd22?a114f (all pins) 7 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the transient voltage is a voltage spike injected to drv pin being in high state. maximum transient duration is 100 ns. 2. see below figure for detailed specification of transient voltage 3. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78.
ncp12600 www. onsemi.com 5 table 3. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) characteristics conditions symbol min typ max unit supply section and v cc management v cc level at which driving pulses are authorized v cc increasing v cc(on) 16 18 20 v v cc level at which driving pulses are stopped v cc decreasing v cc(min) 8.3 8.9 9.5 v start?up hysteresis hysteresis v cc(on) ? v cc(min) v cc(hyst) 7.7 v latched?state reset voltage ? v cc(reset) 8.65 v hysteresis above v cc(min) for fast hiccup v cc(hiccup) 150 mv hysteresis below v cc(min) before reset hysteresis v cc(min) ? v cc(reset) v cc(reset, hyst) 0.18 0.33 0.42 v start?up supply current, controller disabled or latched v cc = v cc(on) ? 100 mv i cc1 ? 5 10 a internal ic consumption, steady state f sw = 65 khz, c drv = 0 nf, v fb = 3.2 v f sw = 100 khz, c drv = 0 nf, v fb = 3.2 v i cc2 ? 1 1.1 ma internal ic consumption, steady state f sw = 65 khz, c drv = 1 nf, v fb = 3.2 v f sw = 100 khz, c drv = 1 nf, v fb = 3.2 v i cc3 ? 1.7 2.3 ma internal ic consumption, skip mode ? non switching feedback voltage is below skip level i cc(no?load) 300 a internal ic consumption in skip mode ? switching in application, for information only (v cc = 12 v, driving a typical 7?a/650?v mosfet, includes optocoupler current) i cc(standby) 420 a internal ic consumption from ovp acknowledgment to v cc(off) ? single?shot event ic detects an ovp and quickly brings v cc to v cc(off) for hiccup i cc(ovp) 1 ma current sense comparator maximum current sense voltage limit ? no opp v fb = v fb(max) , v cs increasing v zcd < ?60 mv (notes 4, 5) v ilim1 0.65 0.7 0.75 v overload current sense voltage threshold ? dual ocp option v fb = v fb(max) , v cs increasing v ilim2 0.46 0.5 0.53 v cycle by cycle leading edge blanking duration t leb1 230 280 340 ns cycle by cycle current sense propagation delay v cs > (v ilim + 100 mv) to drv turn?off t ilim ? 50 100 ns maximum setpoint decrease for pin 3 biased to ?290 mv (note 6) v zcd = ?290 mv iopp m 32.8 % voltage setpoint for pin 3 biased to ?250 mv (note 6) ioppv et 0.46 0.51 0.56 v blanking delay before considering v zcd for opp iopp del 600 ns pin 4 voltage bias for 0% opp v zcd = ?60 mv iopp 0 ?60 mv frozen cs voltage in skip mode v fb = 1 v v freeze 200 mv soft start, time to meet i p,max at start up open feedback pin t ss 5 ms oscillator oscillator frequency ? nominal (65 khz version) 2.4 v < v fb < 3.8 v f osc,nom 61 65 71 khz oscillator frequency ? nominal (100 khz version) 2.4 v < v fb < 3.8 v f osc,nom 90 100 110 khz oscillator frequency ? minimum v fb < 1.3 v f osc,min 23 26 31 khz maximum duty ratio d max 76 % 4. opp is not active as long as the negative voltage on the zcd pin during t on is less than ?60 mv. 5. beyond 3.8 v, the peak current is clamped to v ilim . 6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below ?300 mv.
ncp12600 www. onsemi.com 6 table 3. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) characteristics unit max typ min symbol conditions oscillator frequency jittering in percentage of f osc ccm?only operation f jitter 6 % frequency jitter in valley?switching mode internal offset to cs control f swingdcm 10 mv jitter modulation frequency in all modes ? f swing 1 khz soft?start, time to meet nominal f sw at start up open feedback pin t ss 5 ms internal slope compensation artificial ramp level for slope compensation internal level at t j = 25 c v ramp ? 4.2 ? v internal ramp resistance to cs pin r ramp ? 20.4 ? k feedback section feedback input open voltage fb pin is unloaded v fb(open) 4 v internal current setpoint division ratio ? k ratio ? 5.4 ? ? pull?up resistance ? r fb ? 40 ? k equivalent resistance for the optocoupler ? r eq 29 k frequency foldback threshold, f sw < 65 khz ? v fold 2.3 2.4 2.5 v end of frequency foldback threshold ? v fold,end 1.8 1.9 2 v feedback voltage thresholds for skip mode v fb going down, t j = 25 c v skip(in) 0.9 1.0 1.1 v skip?cycle current in percentage of i lim ? i skip 26 % hysteresis on skip comparator v fb is going up i skip,hys 60 mv quiet skip only minimum number of pulses in burst n p,skip 3 ? ? ? skip out delay t skip ? ? 38 s quiet?skip timer t quiet 1.0 1.25 1.5 ms quiet?skip escape level (transient enhancer) v fb going up, t j = 25 c v skip(tran) 1.8 2 2.2 v demagnetization sense v zcd threshold voltage v zcd decreasing v zcd(th) 25 45 70 mv v zcd hysteresis v zcd increasing v zcd(hys) 30 mv threshold voltage for output short circuit or aux. winding short circuit detection (enter) after t delay_zcd if v zcd < v zcd(short1) v zcd(short1) ? 0.4 ? v threshold voltage for output short circuit or aux. winding short circuit detection (exit) after t delay_zcd if v zcd > v zcd(short2) v zcd(short2) 0.5 v propagation delay from valley detection to drv high v zcd decreasing from 3 v to 0 v t dem ? ? 150 ns internal delay after demagnetization detection t delay 100 ns timeout after last demagnetization transition (leakage ringing blanking) ? t timout 4.5 5.5 6.5 s input leakage current v cc > v cc(on) v zcd = 3 v, drv is low i zcd ? ? 0.1 a low?v in flag activation ? latched ocp version only neg. bias present during the on?time v boin ?22 ?30 ?38 mv drive output drive resistance drv sink drv source r snk r src ? ? 16 22 ? ? 4. opp is not active as long as the negative voltage on the zcd pin during t on is less than ?60 mv. 5. beyond 3.8 v, the peak current is clamped to v ilim . 6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below ?300 mv.
ncp12600 www. onsemi.com 7 table 3. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ?40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) characteristics unit max typ min symbol conditions drive output rise time c drv = 1 nf, from 10% to 90% t r ? 40 ns fall time c drv = 1 nf, from 90% to 10% t f ? 30 ns drv low voltage v cc = v cc(off) + 0.2 v, c drv = 220 pf, r drv = 33 k v drv(low) 8 ? ? v drv high voltage v cc = v cc(ovp) ?0.2 v , c drv = 220 pf, r drv = 33 k v drv(high) 10 12 14 v source current peak source current v gs = 0 v i source 300 ma sink current peak sink current v gs = 12 v i sink 500 ma protections auto?recovery thermal shutdown device switching t shtdn ? 150 ? c thermal shutdown hysteresis device switching t shtdn(hys) ? 40 ? c fault level detection for ovp, demagnetization pin, t off sensing internal sample v out increasing v ovp1 2.85 3.15 3.35 v fault level detection on cs pin for otp implemen- tation ? confirmation delay is t pp internal sample v cs increasing v otp 0.97 1 1.03 v over voltage protection on the v cc pin ? v ovp2 24 25.5 27 v sampling delay for otp and ovp detection (f sw = 65 khz) sampling event on zcd and cs pins t delay_zcd1 1.2 1.5 1.8 s sampling delay for otp and ovp detection (f sw = 100 khz) sampling event on zcd and cs pins t delay_zcd2 0.8 1.1 1.3 s number of drive cycles before latch confirmation on ovp1 and 2 v zcd > v ovp1 t latch_count ? 8 ? ? timer delay before fault acknowledgment ? condition 1 ? single ocp only cs pin is 0.7 v t pp1 55 64 75 ms timer delay before fault acknowledgment in overload condition ? dual ocp only cs pin 0.5 v t ocp 200 256 300 ms timer delay before fault acknowledgment with dual ocp ? dual ocp only cs pin is 0.7 v t pp2 55 64 75 ms timer delay in clock cycles before fault acknowledgment when in output short circuit ? condition 2 v zcd < 0.4 v unit is clock cycles t scp 8 4. opp is not active as long as the negative voltage on the zcd pin during t on is less than ?60 mv. 5. beyond 3.8 v, the peak current is clamped to v ilim . 6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below ?300 mv. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. note: condition 1: v fb is pushed to its maximum open?loop value. the demagnetization pin during the off?time is above 0.4 v. condition 2: v fb is pushed to its maximum open?loop value. the demagnetization pin during the off?time is less than 0.4 v. 8 clock cycles are counted and the part latches off or goes into auto?recovery. this mechanism only activates once the 5?ms soft?start sequence is completed.
ncp12600 www. onsemi.com 8 typical characteristics figure 3. figure 4. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 17.0 17.2 17.6 17.8 18.0 18.4 18.8 19.0 125 100 75 50 25 0 ?25 ?50 8.0 8.2 8.6 8.8 9.0 9.4 9.8 10.0 figure 5. figure 6. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 8.0 8.2 8.6 8.8 9.0 9.4 9.6 10.0 100 75 50 125 25 0 ?25 ?50 8.0 8.1 8.3 8.4 8.5 8.7 8.8 9.0 figure 7. figure 8. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 4.0 4.5 5.0 5.5 6.0 6.5 7.0 100 75 50 125 25 0 ?25 ?50 0.290 0.295 0.300 0.305 0.310 0.315 0.320 v cc(on) (v) v cc(min) (v) v cc(hyst) (v) v cc(reset) (v) i cc1 ( a) i cc no load (ma) 17.4 18.2 18.6 8.4 9.2 9.6 8.4 9.2 9.8 8.2 8.6 8.9 f sw = 65 khz f sw = 65 khz
ncp12600 www. onsemi.com 9 typical characteristics figure 9. figure 10. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0.8 0.9 1.1 1.2 1.3 1.5 1.6 125 100 75 50 25 0 ?25 ?50 2.00 2.10 2.20 figure 11. figure 12. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 0.90 1.00 1.05 1.10 1.15 1.20 100 75 50 125 25 0 ?25 ?50 1.80 1.82 1.86 1.88 1.90 1.94 1.96 2.00 figure 13. figure 14. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 0.290 0.295 0.300 0.305 0.310 0.315 0.320 100 75 50 125 25 0 ?25 ?50 1.09 1.10 1.11 1.12 1.13 1.14 i cc(latch) (fb = 4 v) (ma) i cc(autor) (ma) i cc2_65khz (ma) i cc3_65khz (ma) i ccnoload (ma) i cc2_100khz (ma) 1.0 1.4 2.05 2.15 0.95 1.84 1.92 1.98 f sw = 65 khz f sw = 65 khz f sw = 100 khz
ncp12600 www. onsemi.com 10 typical characteristics figure 15. figure 16. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 2.30 2.34 2.40 125 100 75 50 25 0 ?25 ?50 0.697 0.698 0.700 0.701 0.703 0.704 0.705 figure 17. figure 18. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 0.40 0.50 0.55 0.60 100 75 50 125 25 0 ?25 ?50 275 277 278 279 280 281 figure 19. figure 20. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 3.128 3.133 3.138 3.143 3.153 3.158 3.163 100 75 50 125 25 0 ?25 ?50 0.994 0.996 0.998 1.000 1.002 1.004 1.006 i cc3_100khz (ma) v ilim (v) v olm(0.5) (v) t leb (ns) v ovp1 (v) v otp (v) 2.32 2.36 2.38 0.699 0.702 0.45 276 f sw = 100 khz 3.148
ncp12600 www. onsemi.com 11 typical characteristics figure 21. figure 22. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 25.36 25.46 125 100 75 50 25 0 ?25 ?50 3.80 3.90 3.95 4.00 figure 23. figure 24. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 16.2 17.2 18.2 18.7 100 75 50 125 25 0 ?25 ?50 3.00 3.05 3.15 3.20 3.25 3.35 3.40 3.50 figure 25. figure 26. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 29.0 29.1 29.3 29.5 29.6 29.9 30.0 100 75 50 125 25 0 ?25 ?50 64.0 64.5 65.0 65.5 66.0 66.5 67.0 v ovp2 (v) fb open (v) r ramp (k ) v ramp (v) req (k ) f osc(max) (none) (khz) 125.41 25.51 25.56 3.85 16.7 17.7 3.10 3.30 3.45 f sw = 65 khz 29.8 29.7 29.4 29.2
ncp12600 www. onsemi.com 12 typical characteristics figure 27. figure 28. temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 25.0 25.4 25.6 26.0 26.4 125 100 75 50 25 0 ?25 ?50 99.0 100.0 100.5 101.0 102.0 figure 29. figure 30. temperature ( c) temperature ( c) 100 75 125 50 25 0 ?25 ?50 26.0 26.1 26.3 26.4 26.5 26.7 26.8 27.0 100 75 50 125 25 0 ?25 ?50 78.0 78.2 78.6 78.8 79.0 79.4 79.6 80.0 figure 31. temperature ( c) 100 75 125 50 25 0 ?25 ?50 78.0 78.2 78.6 79.0 79.6 79.8 80.0 f oscmin(65khz) (khz) f osc(100khz) (khz) f oscmin(100khz) (khz) d max(65khz) (%) d max(100khz) (%) 25.2 25.8 26.2 99.5 101.5 26.2 26.6 26.9 78.4 79.2 79.8 f sw = 65 khz f sw = 100 khz f sw = 100 khz 78.4 78.8 79.2 79.4
ncp12600 www. onsemi.com 13 application information the ncp12600 includes a state?of?the?art multi?mode controller packed in a tiny 6?pin package for fixed?frequency current mode control flyback converters applications. despite its limited amount of pins, the controller includes numerous proprietary functions which make it an ideal candidate for cost?sensitive applications. ? fixed?frequency operation: implementing peak current mode control, the ncp12600 drives a flyback converter at a 65?khz or 100?khz fixed switching frequency and can operate in discontinuous conduction mode (dcm) or continuous conduction mode (ccm). ? when dcm operation occurs in fixed?frequency operation, the converter locks in a valley and a specific mechanism paces valley jumps. when the output power reduces, the part enters frequency foldback and jumps into the valleys as the load further reduces. going down to 32 valleys (if available), the part ensures the lowest turn?on losses and enables excellent overall efficiency. as output power further goes down, the voltage? controlled oscillator (vco) takes over and reduces frequency down to 25 khz where the current freezes to 26% of the maximum peak value. then the part enters normal skip cycle at lower power levels or in a no?load situation. ? quiet?skip operation: classical skip cycle occurring in light load is a known mechanism to improve the converter?s efficiency when the load current becomes lighter. quiet?skip also reduces acoustic noise by preventing the skip mode burst period from entering the audible range. the part is also available with a normal skip option. ? temporary and peak power capability: the part includes a 2?level ocp allowing the converter to permanently deliver a certain amount of power as long as v cs is less than 0.5 v. when vcs exceeds 0.5 v, a 256?ms timer is activated. if v fb further increases, the switching frequency remains constant and the controller pushes v cs to its maximum value, the 256?ms ocp timer is instantaneously divided by 4 and becomes a 64?ms timer. when it elapses, the part enters an auto?recovery or latched mode depending on the selected option. as such, the converter can be thermally designed for a 0.5?v v cs and authorizes temporary excursions to a higher power level. please note that the controller also exists in a single ocp level (0.7 v, 64 ms duration).. ? adjustable over power protection (opp): switching power supplies are prone to output power runaway in high?line conditions. to keep the delivered power within control along the input voltage range, a circuit observes the negative voltage present on the demagnetization pin during the on?time and subtracts it from the maximum peak current limit. ? low start?up current: a low start?up current is key to reducing the standby power in no? or light? load situations. w ith a 10? a max guaranteed up to 125 c, the ncp12600 lets you enjoy high?valued start?up resistors for the best standby power performance. ? over voltage protection: by precisely sampling the auxiliary winding plateau voltage after the leakage inductance is damped, the circuit monitors the reflected output voltage with excellent precision. when the monitored voltage exceeds the internal threshold more than 8 successive clock cycles, the part definitively latches off. ? over current protection: when the circuit senses that the feedback loop is lost, v fb > 3.8 v, an internal 64?ms timer counts. if the fault disappears while countdown has started, the timer resets and the power converter keeps operating. if the timer elapses, all pulses are immediately stopped and the part enters an auto?recovery hiccup mode. ? true short?circuit protection: by observing the peak current setpoint and the off?time voltage on the demagnetization pin, the circuit can detect an output short circuit situation. when this conjunction of events is confirmed, the scp timer keeps counting. if this situation is observed for more than 8 clock cycles, the circuit immediately stops pulses and enters auto?recovery or latched state. this circuit is active during a start?up sequence (after ss has completed) and in auto?recovery hiccup: if the demagnetization pin is less than 0.4 v after the soft?start period (peak current is maximum), then 8 cycles are counted and the part stops operations. this is extremely efficient to protect against board?level short circuits occurring at high line as the rcd circuit can fail to keep the v ds withing safe limits. ? a general reset is implemented at too low an input voltage and avoids latch off in line dropout tests with ocp?latched versions of the ncp12600. when v out collapses within a line cycle dropout test, the part does not latch (in case the latched option has been selected) but nicely recovers when the mains is back to its normal level. ? quick reset scheme: when latched on an ovp or an ocp situation, the part will enter a fast low?voltage hiccup mode slightly above the reset voltage. the reset time by input power cycling will be greatly reduced compared to existing solutions. ? frequency jitter: an internal clock modulates the switching frequency and provides an efficient energy spread to ease the converter?s emi signature. jitter
ncp12600 www. onsemi.com 14 operates in fixed?frequency mode but also in qr and foldback modes when the vco is active. ? over temperature protection is implemented by forming a resistive divider on the cs pin. the auxiliary voltage appears during the off time and the cs level is only considered after the 1.5? s blanking time (1.1 s for the 100?khz version). for a well?regulated output voltage, the precision favorably compares with a classical pull?down ntc on a dedicated pin. ? temperature shutdown: the controller includes an internal thermal sensor which protects the circuit in case of thermal runaway. overall description the ncp12600 builds upon previous generations of fixed?switching frequency power suppy controllers. the frequency is fixed in nominal power conditions but reduces as the load is getting lighter. the major improvement lies in the valley?switching operation: when dcm is entered whether it is in high?power mode or in foldback, the controller locks in the valley to ensure the best efficiency. when variable frequency mode is activated, the part locks in valleys and remains in this state. the peak current is free to move at all times. ccm operation in fixed?frequency operation, the part switches at 65 khz or 100 khz in current?mode control and the feedback permanently adjusts the current setpoint. for a feedback voltage beyond 3.8 v, the peak current voltage setpoint is clamped to 0.7 v. the situation with this maximum current cannot last more than 64 ms (t pp ). however, if a true short circuit is detected in the output, the controller could potentially place the conve rter in a dangerous situation if it were pulsing while v out is almost 0 v (heavy ccm can occur in the primary side with a rcd clamp voltage runaway). to avoid this stressful situation, the circuit senses the voltage on the demagnetization pin during t off . if during t off the demagnetization pin voltage is less than 0.4 v for more than 8 consecutive clock cycles, the controller stops all pulses and goes into latch or auto?recovery mode depending on the selected option. if during this mode and before the 8?cycle timer ends, the short circuit disappears and the demagnetization voltage goes above 0.5 v, the protection scheme is reset. dcm operation in fixed?frequency operation, it is very likely that low? and high?line conditions lead to a different operating point for a given p out : ccm in low line and dcm in high line. when the controller operates in ccm, the mosfet is turned on at a pace imposed by the regular clock. when dcm is entered, the controller senses this mode and extends the off?time to exactly match the next available valley. the peak current is free to move while locked in the valley whether the part operates in fixed frequency mode or in foldback. inside the controller, a low?frequency refresh clock (lfc) initiates a valley acquisition and increases or decreases valley count during operations. when the next low?frequency clock occurs, a new valley acquisition is run to determine what valley number matches the upcoming 65?khz (or 100 khz) or vco pulse. it is like a snapshot where you freeze the converter operating point for the upcoming period of time. for example, assume the 1 st valley was selected, then the new acquisition may confirm the 3 rd valley is the correct one and the part locks in valley 3. it remains there until the next acquisition occurs or a transient unlocks the control. that way, jumping between valleys occurs at a controlled recurrence and not in a completely random way, reducing the possibility to excite a mechanical resonance on the transformer. variable frequency mode when the load gets lighter, the feedback voltage starts decreasing. when it reaches 2.4 v, the vco takes over and frequency reduces. when vfb reaches 1.9 v, the frequency is clamped down to 25 khz. below this value, f sw is fixed and down to the skip cycle point, the part operates in peak current mode control. when the frequency reduces, the controller selects the valley next to the vco clock and locks in until the next refresh signal comes from the lfc. by using a 5?bit counter, the controller goes down to the 32 nd valley if necessary. when a transient is detected on the feedback voltage (load re? or disconnection), the lfc disappears and the part returns to a classical fixed?frequency operation for the best transient response. protections there are several types of protection depending on loading conditions: 1. when the load imposes a peak current setpoint greater than 0.7 v, the 64?ms timer starts counting. when it elapses, the converter latches off or enters auto?recovery depending on the selected option. 2. a dual ocp version exists also for peak power capability: when the peak current setpoint reaches 0.5 v, the 256?ms timer starts counting. if the power further increases, v cs also does and touches the 0.7?v limit. at this moment, the timer is divided by 4, authorizing a 64?ms duration in this mode. afterwards, the controller latches off or enters an auto?recovery cycle. 3. in this maximum power mode, the converter observes the demagnetization voltage during t off . if this voltage is lower than 0.4 v and if this situation lasts for more than 8 consecutive clock cycles, the controller immediately stops pulsing and enters auto?recovery or latches off depending on the selected options. 4. during start?up, the controller also observes the demagnetization pin during the off?time. if this voltage is less than 0.4 v once the soft?start sequence is over (peak current is max) while f sw is
ncp12600 www. onsemi.com 15 65 khz (or 100 khz), then the controller counts 8 clock cycles and terminates operation. v cc goes down to uvlo and the ic restarts (hiccup mode) or remains latched (latched version). 5. at any moment when the 64?ms timer circuit is counting, the controller observes a brown?out (bo) flag raised if v zcd is less than v boin . if a condition arises during which the bo flag is raised and any of the timer is counting, all pulses stop but the resulting counter effect (latch for instance) is ignored and v cc is let go down to uvlo for a quick recovery. with this technique, when adapters featuring a latched ocp option are tested in line cycle dropouts, even if the converter would like to latch off because the mains has disappeared while it was heavily loaded, the circuit prevents this and forces the converter to auto recover when the mains is restored.. 6. the part senses the plateau voltage on the demagnetization pin 1.5 s after the power switch has been turned off (1.1 s for the 100?khz version). this helps ignore the leakage ringing and offers a clean plateau voltage to sense. when the voltage on the demagnetization pin exceeds 3.15 v for 8 consecutive clock cycles, the part latches off (or hiccups depending on the selected option). this is an easy and efficient way to protect the converter in an ovp situation. 7. a similar sampling occurs on the cs pin to check if an otp event is detected. when the pin exceeds 1 v during the off time for more than 64 ms, the part latches off (or hiccups depending on the selected option). start?up sequence as illustrated in figure 32, peak current and the switching frequency are gradually increased at start?up in a 5?ms soft?start (ss) sequence. frequency starts from 25 khz and hits 65 khz (or 100 khz) after 5 ms as feedback voltage is pushed to its maximum value. the 64?ms timer counts as v cs is above 0.7 v. when the 5?ms ss sequence is over, the peak current is maximum. during this sequence (v fb is still pushed to the max, v out is not on target), if v cc accidentally touches uvlo, the part featuring the pre?short option immediately latches off. on the contrary, if everything goes well ? the loop closes (v out is on target) before v cc touches uvlo and the 64?ms timer is reset. if an uvlo event occurs after a normal start?up sequence, it auto?recovers as it should. this smooth start?up mode helps reduce the stress on the output diode or in the synchronous mosfet when power up occurs on heavy load. as this mode is also activated in auto?recovery protection (for the selected option), it significantly reduces the stress on the various power components when the converter tries resuming operations. figure 32 offers a typical drive waveform captured during the power?on sequence. () drv vt 40 s 25 khz t on = 1.4 s 25 khz 65 khz 5? ms ss power on figure 32. during the start?up sequence, both frequency and current setpoint are slowly raised for 5 ms the ncp12600 start?up voltage is purposely made high to permit large energy storage in a small v cc capacitor value. this helps operation with a small start?up current which, together with a small v cc capacitor, will not hamper the start?up time. to further reduce the standby power, the controller start?up current is purposely kept low, below 10 a and it is guaranteed up to a 125 c junction temperature. start?up resistors can therefore be connected to the bulk capacitor or directly to the mains input voltage if desired to save a few more mw.
ncp12600 www. onsemi.com 16 d1 d2 d3 d4 input mains cbulk c1 x2 r1 r2 r3 r4 icc1 cvcc d5 1n4148 c4 d6 bav21 aux . vcc i1 i2 i3 figure 33. the startup resistor can be connected to the input mains for further power dissipation reduction figure 33 shows a typical recommended configuration where start?up resistors connect together to the mains input. this technique offers the benefit of freely discharging the x2 capacitor usually part of the emi filter. the calculation of these resistors depends on several parameters. assuming a 0.47? f x2 capacitor, the safety standard recommends a time constant less than 1 s maximum when a resistor is connected in parallel to provide a discharge path. this sets the upper limit for the sum of discharge resistors connected to the controller v cc : r startup 1 0.47 2.1 m (eq. 1) the first step starts with the calculation of the needed v cc capacitor which will supply the controller until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 and 20 ms depending on the loading conditions and the output capacitance. considering that we need at least an energy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: cv cc i cc t 1 v ccon v ccmin 1.5 m 10 m 9 1.6 f (eq. 2) let us first select a 2.2? f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t 1 . testing across temperature range is important as capacitance and esr of this v cc capacitor can be affected. the v cc capacitor being known, we can now evaluate the charging current we need to bring the v cc voltage from 0 to the ic vcc on voltage, 18 v typical. this current has to be selected to ensure start?up at the lowest mains (85 v rms) to be less than 3 s (2.5 s for design mar gin) typically for an adapter: i charge v ccon c v cc 2.5 18 2.2 2.5 16 a (eq. 3) if we account for the 10? a current that flows inside the controller ( i 1 in figure 33), then the total charging current delivered by the start?up resistor must be 26 a, rounded to 30 a. if we connect the start?up network to both mains inputs (two half?wave connections then), half of the average current i 1 is defined by: i 1 2 v ac,rms 2 v ccon r startup (eq. 4) to make sure this current is always greater than 15 a (half of the necessary 30? a current), the minimum value for r start?up can be extracted: r start?up v ac,rms 2 ?v ccon i cv cc ,min 85 1.414 ?18 15 1.3 m (eq. 5) we could thus connect two resistors of 1.3 m (total 2.6 m ) across the line to a) power the ic at start up b) ensure x2 discharge when the user unplugs the adapter. however, 2.6 m conflicts with (1) and we will reduce the 1.3?m resistor to a 1?m value, totaling 2 m , in agreement with (1). multi?mode operation the ncp12600 works as a classical fixed?switching frequency controller and can operate in ccm and dcm. when the load current is reducing, the converter eventually enters dcm. at this moment, ncp12600 implements a proprietary multimode engine which locks in the drain?source vall ey to improve ef ficiency. the frequency is now fixed but the peak current is free to move to maintain v out in regulation. an internal refresh clock will start a new acquisition and valley jump occurs but at a controlled pace. this operation differs from other controllers in which the selected valley changes on the fly, resulting in a spectrally?distributed perturbation. this uncontrolled perturbation can possibly mechanically excite the transformer and generate acoustic noise. here, because the refresh frequency is constant, it is less likely to excite the transformer across a variety of frequencies and acoustic noise is eliminated in this mode. in case a transient load occurs, the controller naturally returns to its normal operating mode until the feedback stabilizes again.
ncp12600 www. onsemi.com 17 () ds vt () ds vt () ds vt 3 rd to 2 nd jump from 3? 2? 3 valleys v in = 142 v, i out = 0.9 a figure 34. the multimode engine paces the valley jump event at a controlled rate over power and over voltage protection over power protection (opp) is a known means to limit the output power excursion at high mains. several elements such as propagation delays and operating mode explain why a converter operated at high line delivers more power than at low line. ncp12600 implements a proprietary technique that senses the bulk input voltage via a resistive network connected to the auxiliary winding. however, as the pin used for opp (pin 3) also combines other functions such as demagnetization detection and ovp, a specific network has to be designed as shown in figure 35. rzcd ropp rupp . 3 aux winding d1 bav21 figure 35. over power protection is provided via the bulk voltage image present on brown?out pin during t off , the auxiliary winding jumps to the reflected output voltage scaled by the secondary?to?auxiliary transformer turns ratio. diode d 1 is conducting and the network r upp / r zcd sets the ovp voltage. when the power mosfet turns on, the auxiliary voltage jumps to a negative voltage representative of the input voltage. that negative voltage will be internally subtracted from the peak current setpoint. an internal 60?mv offset prevents compensation from taking place at low line. the positive and negative auxiliary voltages depend on the transformer turns ratios. we can define them as follows: n p :n s = n pow , the primary to power winding turns ratio n p :n a = n aux , the primary to auxiliary winding turns ratio during the off?time, the auxiliary winding jumps to the following plateau voltage: v aux v out
v f 1 n aux n pow (eq. 6) in which v f 1 is the power diode drop at nominal power. that voltage appears on pin 3 affected by the resistive divider r upp / r zcd and d 1 ?s forward drop v f 2 : v plat v aux
v f 2 r zcd r zcd
r upp (eq. 7) during the on?time, d 1 is blocked and r opp now appears in series with r upp . the voltage on pin 3 is defined as
ncp12600 www. onsemi.com 18 v pin3 r zcd r zcd
r upp
r opp n aux v in (eq. 8) in which v in is the bulk dc voltage. that voltage is the negative opp voltage we need for our compensation. as pin3 internally includes a 60?mv offset, the negative voltage present on pin3 brings a final sense voltage reduction of v sense 700 mv
v pin3
60 m (eq. 9) assume v pin3 = ?150 mv during t on , thus the effective sense reduction is v sense 700 mv 150 m
60 m 610 mv (eq. 10) the peak current reduction is thus 12.8%. combining the above equations lets us calculate the values for r upp and r opp based on design requirements: r opp r zcd v f 2 n aux v f 1
v ovp n pow v ovp1 n aux r zcd v inhl v opp (eq. 11) r upp r zcd n aux v f 1
v ovp n pow v f 2 v ovp1 r zcd (eq. 12) in these expressions, we have: r zcd is the pull?down resistor arbitrarily selected. 1.8 k could be a value to start with (we recommend to select a resistance below 2 k for the best linearity in the opp compensation) v ovp is the output voltage at which you want the plateau to reach the threshold voltage v ovp1 (3.15 v typical) v inhl is the high?line dc voltage measured across the input bulk capacitor assume the following data: v out = 19 v, n pow = 0.250, n aux = 0.184, v f1 = 0.8 v, v f2 = 0.65 v, v inhl = 375 v, r zcd = 1.8 k we want an opp reduction of 12% and an output ovp set to 25 v. this leads to the following resistor values: r upp = 9.2 k and r opp = 851 k . pin3 is also used for demagnetization detection. a small capacitance can be added in parallel with r zcd to introduce a delay and to exactly turn?on in the drain?source valley. experiments show that capacitances up to 150 pf provide adequate results. please make sure the negative value during the on?time is not affected by too large a capacitance. pin3 protects the converter against short circuit to ground. should you do this during safety tests, the part simply interprets the shortening to ground as an output short circuit and stops pulsing quickly. please note that an excel ? spreadsheet is available from our product website and automates the calculation of the above resistances. slope compensation the ncp12600 includes an internal slope compensation signal. this is the buf fered oscillator clock deliver ed during the on?time only. its amplitude is around 4.2 v at the maximum duty ratio. slope compensation is a known means used to eliminate sub?harmonic oscillations in ccm? operated current?mode converters. these oscillations take place at half the switching frequency and occur only during ccm with a duty ratio greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. figure 36 depicts how internally the ramp is generated. please note that the ramp signal will be disconnected from the cs pin, during the off time. rsense rcomp 20k 0v 2.5 v cs + ? l.e.b from fb setpoint latch reset on 4.2 v 20.4 k figure 36. inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in ccm operation ncp12600 oscillator ramp features a 4.2 v swing. if the clock operates at a 65?khz frequency, then the available oscillator slope corresponds to: s ramp v ramp,peak d max t sw 4.2 0.8 15.4 341kv s or 341mv s (eq. 13) in our flyback design, assume a primary inductance l p of 550 h. the converter delivers 19 v with a n p : n s ratio of 1:0.25. the of f?time primary current slope s p is thus given by: s p v out
v f 1 n s n p l p ( 19
0.8 ) 4 550 u 144 ka s (eq. 14) considering a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 144 k 0.33 47 kv sor47mv s (eq. 15) if we select 50% of the downslope as the required amount of compensation, then we shall inject a ramp whose slope is
ncp12600 www. onsemi.com 19 23 mv/ s. our internal compensation being of 341 mv/ s, the divider ratio ( divratio ) between r comp and the internal 20.4?k resistor is: divratio 23 m 341 m 0.067 (eq. 16) the series compensation resistor value is thus: r comp r ramp divratio 20.4 k 0.067 1.4 k (eq. 17) a resistor of the above value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small capacitor of 100 pf, from the current sense pin to the controller ground for an improved immunity to the noise. please make sure both components are located very close to the controller. feedback the feedback is done by bringing the fb pin down with an optocoupler as shown in figure 37. to maintain a low consumption current, the resistive network on the fb pin is higher than in other controllers. as a result, the optocoupler pole may be located at a lower position. popular optocouplers like pc817 or sfh615 exhibit poles in the 3?4 khz region. for that reason, a simple 100?pf capacitor connected between the circuit fb and gnd pins (located close to the ic) will ensure local decoupling without interfering with crossover selection. in the secondary side, the figure shows a typical application for a 19.5?v output. this is a type 2 configuration and a single 0.1? f capacitor will do the job typically for a fast and non?ringing transient response. 12 3 vdd fb + ? 5 6 cs pwmrst gain 7 buffer 9 vcooutput vco r1 40k r2 135k r3 31k 0.7 v c1 100pf 8 r4 1k 10 r5 10k 11 ncp431 14 r6 56k r7 10k c2 0.1uf r8 12k vout 19.5 v figure 37. the optocoupler brings the fb pin down as the ncp431 injects more current into the led the ncp12600 is a multi?mode controller meaning that several operating modes are possible: 1. continuous conduction mode (ccm) is available as with any pwm controller. usually, ccm is entered at heavy load and low line. 2. as output power reduces, the converter leaves ccm and enters discontinuous conduction mode (dcm). the controller detects this mode and locks in the next available valley. the switching frequency is no longer fixed and is dictated by the valley jumps. the feedback voltage can be between its maximum value and 2.4 v in this quasi?resonant mode. discrete frequency jumps occur but are controlled by ncp12600 internal logic. 3. if the load current continues to decrease, the feedback passes below the 2.4?v threshold and frequency foldback begins. the frequency is gradually reduced from 65 khz (or 100 khz) to 25 khz. this low?frequency value is reached when v fb reaches 1.9 v. when the voltage?controlled oscillator (vco) operates, the controller also locks in the valley to ensure the best efficiency. valley jumping is also likely to occur here but the controller sets the pace at which they occur. of course, nothing prevents from finding a stable operating point between two hesitations, this is normal. 4. the load current is very small and the feedback voltage is below 1.9 v. frequency is fixed to 25 khz and classical peak current mode control operates. when the feedback voltage touches 1 v, classical or quiet skip cycle takes place for the best standby power performance. see below for detailed operations. the curve in figure 38 describes the various operating stages as feedback varies.
ncp12600 www. onsemi.com 20 out p sw f 65 khz 25 khz sense v out p 1v fb v < pwm operation with fixed f sw v fb = 3.8 v v fb = 4 v 0.7 v timer starts pwm operation with fixed f sw foldback zone with jitter v fb = 2.4 v v fb = 1.9 v open-loop full load figure 38. the frequency is folded back as output power demands reduces dual ocp ? option some applications require the possibility to deliver a peak power during a certain duration while the rest of the time, the average power is low. the converter is thus thermally sized to cope with a moderate average power (v cs < 0.5 v) while allowing short?duration output power peaks when v cs touches the 0.7?v limit. the ncp12600 can be configured in a so?called dual?ocp mode where a second level is inserted in the current sense circuitry. when the voltage on the cs pin crosses this first 0.5?v threshold, a timer of duration t 1 starts. if the power keeps increasing and pushes the peak current to the next 0.7?v sense voltage limit, the charging current of the timer is multiplied by 4 making the new timer t 2 equal to t 1 /4. for instance, a typical timer configuration of 256 ms/64 ms lets the converter delivers power for 256 ms when v cs hits 0.5 v and this time is reduced to 64 ms if it directly jumps to 0.7 v during an overload condition. out p sw f intermediate load 65 khz 25 khz sense v out p 1v fb v < pwm operation with fixed f sw v fb = 3.8 v v fb = 4 v 0.7 v 0.5 v 256 ms timer starts 64 ms timer starts v fb = 2.7 v pwm operation with fixed f sw foldback zone with jitter v fb = 2.4 v v fb = 1.9 v open-loop full load figure 39. the dual?ocp option sets two timers depending on the amount of delivered current quiet?skip ? option to further avoid acoustic noise, the circuit prevents the burst frequency during skip mode from entering the audible range by limiting it to a maximum of 800 hz. this is achieved via a timer t quiet that is activated during quiet?skip. the start of the next burst cycle is prevented until this timer has expired. as the output power decreases, the switching frequency decreases. once it hits minimum switching frequency f osc(min) , the skip?in threshold is reached and burst mode is entered ? switching stops as soon as the current drive pulses ends ? it does not stop immediately.
ncp12600 www. onsemi.com 21 once switching stops, fb will rise. as soon as fb crosses the skip?exit threshold, drive pulses will resume but the controller remains in burst mode. at this point, a 1250 s (typ) timer t quiet is started together with a count to n p, s k i p pulses counter. this n p, s k i p pulses counter ensures the minimum number of drv signal pulses in burst. the next time the fb voltage drops below the skip?in threshold, drv pulses stop at the end of the current pulse as long as n p, s k i p drive pulses have been counted (if not, they do not stop until the end of the n p, s k i p ?th pulse). they are not allowed to start again until the timer expires, even if the skip?exit threshold is reached first. it is important to note that the timer will not force the next cycle to begin ? i.e. if the natural skip frequency is such that skip?exit is reached after the timer expires, the drive pulses will wait for the skip?exit threshold. this means that during no?load, there will be a minimum of n p, s k i p drive pulses, and the burst?cycle period will likely be much longer than 1250 s. this operation helps to improve efficiency at no?load conditions. in order to exit burst mode, the fb voltage must rise higher than v skip(tran) level. if this occurs before t quiet expires, the drive pulses will resume immediately ? i.e. the controller won?t wait for the timer to expire. figure 40 provides an example of how quiet?skip works, while figure 41 shows the immediate escape from quiet?skip if v fb crosses the transient level v skip(tran) . drv drv pulses does not start because v fb v skip(out) in the quiet skip mode v fb v skip(tran) n p , skip n p , skip n p , skip when v fb >v skip(tran) the quiet skip mode immediately finishes quiet skip mode forces at least n p,skip pulses in skip mode burst n p , skip n p , skip running just above skip mode with f sw =f osc(min) figure 40. leaving the quiet?skip mode during load transient v fb time drv enters skip enters skip exits skip after quiet timer expires crossing the transient enhancement level stops the quiet skip immediatelly v skip(in) v skip(out) v skip(tran) t quiet t quiet figure 41. quiet?skip timing diagram
ncp12600 www. onsemi.com 22 over temperature protection it is possible to trip a second protection via the cs pin. if you connect a ntc resistor from the auxiliary winding through a fast diode and a series resistance, it is possible to latch off the part (or make it auto?recover depending on the selected option) at the desired temperature. figure 42 shows the adopted principle. the auxiliary winding jumps to the output voltage reflected to the primary side during t off and described by (6) if the loop is well designed, i.e. with sufficient loop gain in dc, the precision of this available voltage can be very good. as this voltage is available during the off?time, we can use it to build a temperature?dependent voltage on the cs pin and compare the value to an internal precise 1?v reference. according to figure 42 labels, the voltage at the cs pin during t off equals v cs v aux v f 2 r ramp r ramp
r ntc
r otp (eq. 18) the ramp resistor r ramp is selected depending on the operating mode at low line while r otp must be calculated as r otp r ramp v aux v f 2 v otp r ramp r ntc (eq. 19) a very popular ntc model is the tt3 series. assume we have selected a device exhibiting a 470?k resistance at 25 c. when the temperature reaches 110 c, this resistance drops to 8.8 k typically. statistical analysis show that a good precision can be obtained as long as the ramp resistance is of moderate value. here, experiments show that a 1?k resistance is a good fit to the application and leads to the following r otp calculation: r otp 1k ( 14 0.35 ) 1 1k 8.8 k 4.1 k (eq. 20) the ncp12600 reference voltage v otp is guaranteed at 3% across the entire temperature range while all resistors are 1%. the auxiliary plateau is estimated to a 5% precision. the v f of the series diode can be calibrated at the trip point to refine calculations but if the auxiliary winding is of large amplitude, its contribution to the final error remains small. + ? rotp rntc rramp rsense votp . otp cs drv bav21 figure 42. the ntc lifts the cs pin voltage during the off?time. if the voltage exceeds 1 v, all pulses stop we can estimate what the final spread will be in the temperature trip point by assigning uniform distributions to each of the parameters. the resulting curve shown in figure 43 indicates that an ntc resistance varying between 7.6 k and 10 k will trip the controller in otp. 710 3 ? 810 3 ? 910 3 ? 110 4 ? 1.1 10 4 ? 50 100 150 200 r ntcdisti 1 r ntcdisti 0 7.6k ntc r = 10k ntc r = figure 43. by assigning precision to the various components, it is possible to calculate the otp trip point dispersion
ncp12600 www. onsemi.com 23 if we now look at the corresponding temperatures the ntc resistance varying between these two limits correspond to, we obtain a range between 116 and 104 c. centered at 110 c, it gives a theoretical precision of 5.4 c. it is possible to improve the precision by removing the r otp resistor. that element is inserted because the ramp resistance is imposed before the otp calculation. now assume that you remove r otp and calculate r ramp to match the 1?v trip point when r ntc = 8.8 k . in our example, r ramp would be 680 . considering a 2?element divider versus 3 as originally selected, then the dispersion would narrow down to 8 k ? 9.6 k , leading to a temperature trip point of 110 c 4.5 c. something worth considering if the converter requires less slope compensation (light ccm operation) or works exclusively in dcm. latched mode when the part latches off in ovp or otp (or even in an ocp condition if the option is selected), the part immediately stops pulsing and activates an internal 1?ma current source. this source brings v cc quickly to the uvlo level +100 mv and a fast hiccup around uvlo starts. that way, if the user cycles the input source, reset occurs at a quicker pace. figure 44 shows a typical waveform inherent to this proprietary techniques. () ds vt () cc vt fast hiccup 1? ma source is on 1? ma source is off figure 44. when the controller latches off, the v cc is quickly discharged to the fast hiccup level, authorizing a fast reset please note that another ovp is installed on the v cc pin and monitors the dc value permanently biasing the pin. if that voltage exceeds v ovp2 typically set at 25 v the part latches off or auto?recovers depending on the selected option.
ncp12600 www. onsemi.com 24 package dimensions case 318g?02 issue v 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e recommended note 5 l c m h l2 seating plane gauge plane detail z detail z 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters m style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 ncp12600/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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